Apparatus for carrying out serial control

ABSTRACT

An apparatus for carrying out serial control includes a single main controller and a plurality of node controllers for directly controlling a variety of sensors and actuators. The node controllers are serially connected to the main controller. The main controller receives a data signal row which is successively transferred through the node controllers and then indirectly and centrally controls sensor data derived from the sensors, as well as actuator control data transmitted to the actuators. Data is transmitted from the data signal row to the sensors or the actuator to be controlled and vice versa in each node controller. An error code is added to the data signal row which is to be transferred to a succeeding port under logic conditions indicating the occurrence of an error. The occurrence of an error is confirmed by inspecting an error check code which is previously added to the data signal row to check whether an error has or has not occurred between the node controllers. The error code for indicating the occurrence of error is added to the data signal row which is inputted into the relevant node controller.

TECHNICAL FIELD

The present invention relates generally to an apparatus for carrying outserial control wherein the apparatus is preferably employed forcentrally controlling a number of various sensors and actuators used forvarious kinds of industrial machines, numerically controlled machines,unmanned conveying vehicles, robots or the like with the aid of a maincontroller included in a controller for the purpose of controlling theapparatus. More particularly, the present invention relates to anapparatus for carrying out serial control of the type including aplurality of node controllers corresponding to the sensors and theactuators to directly control them. Each of the node controllers isserially connected to the main controller, wherein structure of eachnode controller favorably employable for monitoring an occurrence oferror between the node controllers as well as a protocol fortransmitting signals are practically realized.

BACKGROUND ART

FIG. 10 is a block diagram which schematically illustrates the wholestructure of the apparatus of the above-described type for carrying outserial control.

In FIG. 10, reference numeral 10 designates a machine controller servingas a controller for totally controlling a certain machine for which theapparatus is arranged. Reference numerals 21 to 2n designate sensors oractuators disposed in predetermined locations in the machine. Referencenumeral 30 designates a main controller disposed adjacent to the machinecontroller 10 to serve as central controlling means for the sensors oractuators 21 to 2n. Reference numerals 41 to 4n designate nodecontrollers disposed in correspondence to the respective sensors oractuators 21 to 2n to intermediately process various data (sensor dataor actuator control data) between the node controllers 41 to 4n and themain controller 30, respectively. Usually, with such an apparatus forcarrying out serial control as described above, the main controller 30and the node controllers 41 to 4n are serially connected to each otherin a loop-shaped configuration, as shown in FIG. 10.

FIGS. 11a-11c illustrate by way of example a plurality of protocols fortransmitting a series of signals S0 to Sn between the main controller 30and the node controllers 41 to 4n in the apparatus of the presentinvention.

Specifically, according to this example, each of the signals S0 to Snincludes a data row comprising a row of sensor data indicative of asensor output from each sensor or a row of control data indicative ofthe content of control for controlling a manner of driving eachactuator, a start code for indicating the head end of the data row, thestart code being located upstream of the data row and having apredetermined logical structure represented by plural bits (e.g., eightbits), a stop code for indicating the tail end of the data row, the stopcode being disposed downstream of the data row and likewise having apredetermined logical structure (which is different from the logicalstructure of the start code) represented by plural bits (e.g., eightbits), and an error check code independently generated at each nodecontroller for the purpose of searching for an occurrence of errorbetween respective ports (between respective node controllers), theerror check code being disposed downstream of the stop code to be addedas a code signal having a predetermined number of bits (e.g., 16 bits).The main controller 30 and the node controllers 41 to 4n are informed ofthe presence of data (data row) based on detection of the start code andthe stop code. In addition, the main controller 30 and the nodecontrollers 41 to 4n are informed of an occurrence of error based oninspection of the error check code (to be conducted in accordance with aCRC checking process, a vertical/horizontal parity checking process orthe like process).

With such latter-described apparatus for carrying out serial control,signals are transmitted between the main controller and the nodecontrollers, whereby transmission of data from the main controller tothe node controllers and vice versa, as well as error checking, caneffectively be accomplished without fail. However, when an occurrence oferror is confirmed and transmitted to a node controller at the nextstage or the central main controller 30, the following problems arisedepending on the type signals which are transmitted.

The problems will be exemplified below with reference to FIG. 10 andFIG. 11 on the assumption that an error occurs during transmission ofsignals (data) between a node controller 41 and a node controller 42.Incidentally, T₀₀, T₀₁, T₁₁, T₁₂ and T₂₂ in FIG. 11 represent a time,respectively.

(1) Case where a series of signals S0 to Sn are transmitted betweenrespective node controllers with time delay equivalent to a length ofthe respective signals in each node controller, i.e, in the exampleshown in FIG. 11, the respective times as noted above are set inaccordance with a relationship represented by T00<T01=T11 T12=T21<T22

In this case, e.g., a signal S1 is fully inputted into the nodecontroller 42 from the node controller 41 and it is then delivered to anode controller 43 as a signal S3. Therefore, in this case, the nodecontroller 41 can check an occurrence of error between the nodecontroller 41 and the node controller 42 without fail. Thus, it ispossible to undertake a processing as represented, e.g., by the wording"stop outputting of signals", the wording "send a signal for informingan occurrence of error" or the like wording. In this case, however, datadelay equivalent to a time (T₀₁ -T₀₀) is caused between all the nodecontrollers, resulting in substantially reduced data transmissionefficiency.

(2) Case where a series of signals S0 to Sn are transmitted without timedelay at each node controller, i.e., in the example shown in FIG. 11,the respective times noted above are set in accordance with arelationship represented by T00=T11=T21 or T11<T01 and T21<T12

In this case, e.g., the node controller 42 outputs a signal S2 to thenode controller 43 without any interruption, before a signal S1outputted from the node controller 41 is fully inputted into the nodecontroller 42. Therefore, in this case, the aforementioned time delaycan be reduced. On the other hand, when the node controller 42 checksand confirms an occurrence of error between the node controller 41 andthe node controller 42, this means that inputting of the signal S2outputted from the node controller 43 into the node controller 42 hasbeen started or completed. After all, information of the occurrence oferror to any one of node controllers located downstream of the nodecontroller 43 can not be carried out satisfactorily. Consequently, thereis a high level of possibility that actuators arranged corresponding tonode controllers located downstream of the node controller 43 mayoperate incorrectly or sensors arranged corresponding to any one of nodecontrollers located upstream of the node controller 41 may provideincorrect information.

The present invention has been made with the foregoing background inmind and its object resides in providing an apparatus for carrying outserial control wherein an occurrence of error can reliably be informedto a node controller at the next stage as well as a main controllerwithout reduction of an efficiency for transmitting data.

DISCLOSURE OF THE INVENTION

According to the present invention, each node controller is providedwith at least means for adding an error code for informing an occurrenceof error to a signal outputted from the node controller under logicalconditions that the occurrence of error is confirmed by inspecting anerror check code and that the signal inputted into the node controlleris added with an error code for informing an occurrence of error.

With such construction, even in a case where signals are transmittedwithout time delay in a certain node controller, an occurrence of erroris confirmed in the node controller based on inspection of the errorcheck code and thereafter signals outputted from all the nodecontrollers are added with an error code, respectively. Consequently, anoccurrence of error is reliably informed to all the node controllerlocated downstream of the foregoing node controller and a maincontroller without reduction of a data transmission efficiency.

BRIEF DESCRIPTION OF THE INVENTION

FIG. 1 is a block diagram which schematically illustrates by way ofexample each node controller for an apparatus for carrying out serialcontrol in accordance with an embodiment of the present invention.

FIG. 2 shows a plurality of timing charts each of which illustrates byway of example operations to be performed by the node controller shownin FIG. 1.

FIG. 3 shows a plurality of schematic views each of which illustrates byway of example a protocol for transmitting signals between the nodecontrollers for the apparatus in accordance with the embodiment of thepresent invention.

FIG. 4 is a block diagram which schematically illustrates by way ofexample each node controller for an apparatus for carrying out serialcontrol in accordance with other embodiment of the present invention.

FIG. 5 shows a plurality of timing charts each of which illustrates byway of example operations to be performed by the node controller in FIG.1.

FIG. 6 shows a plurality of schematic views each of which illustrates byway of example a protocol for transmitting signals between the nodecontrollers shown in FIGS. 4 and 5.

FIG. 7 is a block diagram which schematically illustrates by way ofexample each node controller for an apparatus for carrying out serialcontrol in accordance with another embodiment of the present invention.

FIGS. 8 and 9 show a plurality of timing charts each of whichillustrates by way of example operations to be performed by the nodecontroller in FIG. 7, respectively.

FIG. 10 is a block diagram which schematically illustrate structure ofan apparatus for carrying out serial control to which the presentinvention is applied.

FIGS. 11a-11c shows a plurality of schematic views each of whichillustrates a protocol for transmitting signals wherein the protocol isusually employed for the apparatus in FIG. 10.

BEST MODE FOR CARRYING OUT THE INVENTION

Now, the present invention will be described in detail hereinafter withreference to the accompanying drawings which illustrate preferredembodiments thereof.

FIGS. 1 to 3 schematically illustrate an apparatus for carrying outserial control in accordance with an embodiment of the presentinvention, respectively.

Specifically, FIG. 1 illustrates by way of example respective nodecontrollers 41 to 4n on the assumption that the apparatus for carryingout serial control is basically constructed as shown in FIG. 10. Itshould of course be understood that all the node controllers 41 to 4nare constructed in the same way.

As shown in FIG. 1, each of the node controllers 41 to 4n basicallyincludes an input circuit 401 into which a series of signals(hereinafter referred to as a signal row or data signal row) transmittedfrom a central main controller 30 or a node controller at the precedingstate are inputted and they are then demodulated as required, a startcode detecting circuit 402 for detecting from the inputted/demodulatedsignal row a start code representative of the head end of the data rowbased on a predetermined logical structure, an error checking circuit403 for inspecting whether an error occurs between the preceding stage(preceding port) and the present stage (present port) or not, based onan error check code in the inputted/demodulated signal row (the errorcheck code being generated and outputted as a code for searching forpresence or absence of an error) via an error checking code generatingcircuit 407 (to be described later) in the node controller at thepreceding state), an error code detecting circuit 404 for monitoringwhether or not an error code for informing an occurrence of error (theerror code being generated and added via an error code adding circuit408 to be described later) in response to detection of the occurrence oferror is added to the inputted/demodulated signal row and, in a casewhere the error code has been added thereto, informing this fact, an ORcircuit OR for taking a sum of an output derived from detection of anerror by the error checking circuit 403 and an output derived fromdetection of an error code by the error code detecting circuit 404, adata converting circuit 405 for converting data between theinputted/demodulated signal row (exactly speaking, a data row in theinputted/demodulated signal row) and a plurality of sensors or actuators21 to 2n, the data converting circuit 405 generating and outputtingsensor data to be transferred from the present stage based on a sensoroutput from the corresponding sensor, in a case where the sensors 21 to2n are employed for the node controllers 41 to 4n, and generating andoutputting a driving signal for driving the actuators based on controldata to be delivered to the corresponding actuator, in a case where theactuators 21 to 2n are employed for the node controllers 41 to 4n, astop code detecting circuit 406 for detecting a stop code representativeof the tail end of the data row with a predetermined logical structurefrom the inputted/demodulated signal row having sensor data addedthereto or actuator control data removed therefrom via the dataconverting circuit 405, an error check code generating circuit 407 fornewly generating and outputting an error check code based on theinputted/demodulated signal row (output from the data convertingcircuit), a first switch circuit SW1 for controlling an input of theinputted/demodulated signal row (output from the data convertingcircuit), an error code adding circuit 408 for generating the error codeand adding the error code to the inputted/demodulated signal row (outputfrom the data converting circuit) as required (in response to selectionof a second switch circuit SW2 to be described later), a second switchcircuit SW2 for selectively outputting any one of theinputted/demodulated signal row (output from the data convertingcircuit), the signal generated and outputted from the error check codegenerating circuit 407 (error check code) and the signal outputted fromthe error code adding circuit 408 (error code) as time elapses, and anoutput circuit 409 for modulating the signal row selected and outputtedfrom the second switch SW2 as required and delivering the signal row tothe node controller at the next stage or the main controller 30.

Here, the input circuit 401 is constructed to include an inpedancematching circuit, an input amplifier, a demodulating circuit or the likecomponent, in a case where transmission of signals from one nodecontroller to another node controller and vice versa is carried out byelectrical communication via metallic cables (twice pair cables, coaxialcables or the like cables). Further, the input circuit 401 isconstructed to include an photo-electric converter and a demodulatingcircuit (Manchester demodulating circuit, CMI demodulating circuit orthe like circuit), in a case where transmission of signals from one nodecontroller to another node controller and vice versa is carried out byoptical communication via optical fibers.

On the other hand, the output circuit 409 is constructed to include aconverting circuit and a driver circuit, in a case where transmission ofsignal from one node controller to another node controller and viceversa is carried out by electrical communication. Further, the outputcircuit 409 is constructed to include a converting circuit and anelectrical-optical converter, in a case where transmission of signalsfrom one node controller to another node controller and vice versa iscarried out by optical communication.

The error checking circuit 403 is provided in the form of a well-knowncircuit adapted to check errors in accordance with a CRC checkingprocess, a vertical/horizontal parity checking process or the likeprocess.

It should be noted that detailed structure of circuits required forallowing the data converting circuit 405 to transmit data from onesensor or actuator to another sensor or actuator of the sensors oractuators 21 to 2n and vice versa and execute adjustment or the likeoperation in response to transmission of data from one sensor oractuator to another sensor or actuator of the sensors or actuators 21 to2n and vice versa is not shown in FIG. 1 for the purpose ofsimplification of illustration.

FIG. 2 shows a plurality of timing charts which illustrate by way ofexample operations to be performed by the node controller 42 among aplurality of node controllers 41 to 4n. Signal processing operations tobe executed at each node controller will be described below in moredetails with reference to FIG. 2. As will be apparent from FIG. 2,according to the embodiment of the present invention, a method ofcarrying out signal transmission at each node controller without anytime delay is employed for the apparatus. Also in a case of theforegoing method, it is presumed that an error occurs during signaltransmission between the node controller 41 and the node controller 42.

Now, it is assumed that signal transmission is carried out from a nodecontroller at the preceding stage (node controller 41) to a nodecontroller at the next stage (node controller 42) in such a manner asshown in FIG. 2(a). The start code detecting circuit 402 detects a startcode representative of an input signal row in a timing relationshipshown in FIG. 2(b) to control a shifting operation for shifting thefirst switch circuit SW1 to ON (it should be noted that the first switchcircuit SW1 is shifted to OFF at the initial time) (see FIG. 2(g)).Then, the error check generating circuit 407 starts an operation forgenerating an error check code to be transmitted to a node controller atthe next stage (node controller 43) based on the signal row (mainly,data row) which has been inputted thereinto. Incidentally, at this time,the second switch circuit SW2 is held in the initial state as shown inFIG. 2(h), i.e., state wherein inputting via a terminal 1 is selected.Thus, the start code and the data row are added to the output circuit409 via the second switch circuit SW2 as they are left unchanged,whereby they are outputted and transferred as a signal S2 to the nodecontroller at the next stage (node controller 43) via the output circuit409 (see FIGS. 2(h) and (i)). In the meantime, the data convertingcircuit 405 executes an operation for converting data among thecorresponding sensors or actuators.

Next, the thus transmitted signal row is detected by the stop code in atiming relationship shown in FIG. 2(c).

When the stop code detecting circuit 406 detects the stop code in thatway, it carries out control such that the first switch circuit SW1 isturned off to assume the initial state and the second switch circuit SW2is shifted to assume a state wherein inputting via a terminal 2 isselected (see FIGS. 2(c), (g) and (h)).

In response to the shifting operation of the second switch circuit SW2,the error check code 2 which has been newly generated in the error checkcode generating circuit 407 is selected and outputted from the secondswitch circuit SW2 subsequent to the stop code which has been alreadydetected so that it is transferred further via the output circuit 409(see FIG. 2(i)).

At the same time as the aforementioned operations, the error checkcircuit 403 executes an inspecting operation with respect to the errorcheck code (error check code 1) which has been transferred from the nodecontroller at the preceding stage (node controller 41). As a result, ifno data error occurs, no signal is outputted from the error checkcircuit 403. As is presumed here, in a case where an occurrence of erroris confirmed by the error check code 1, an error detecting signal havinga logical "1" level is outputted from the error checking circuit 403 fora short period of time at the same time when the occurrence of error hasbeen confirmed (see FIG. 2(d)). Therefore, an output from the OR circuitOR has a logical "1" level for the foregoing period of time (for aperiod of time when the error detecting signal has been outputted). Anoutput from the OR circuit OR is added to the second switch circuit SW2from the error check code generating circuit 407 together with an errorcheck code outputting completion signal which has been transmitted oncompletion of outputting of the error check code generated by the errorcheck code generating circuit 407 (see FIGS. 2(i) and (e)).

The second switch circuit SW2 is provided in the form of a switchcircuit of which shifting operation is controlled in dependence on thepresent logical level representative of a signal to be transmitted fromthe OR circuit OR, under a condition that a signal representative ofcompletion of outputting of generated error check code is transmittedfrom the error check code generating circuit 407, in such a manner that,if a logical level representative of a signal to be transmitted from theOR circuit OR remains at a logical "0" level, the present operativestate is shifted to the initial state, i.e., a state wherein inputtingvia the terminal 1 is selected and, if the logical level remains at alogical "1" level, the present operative state is shifted to assume astate wherein inputting via a terminal 3 is selected. Therefore, in thiscase, the second switch circuit SW2 is shifted to assume a state whereininputting via the terminal 3 is selected at the same time when an errorcheck code outputting completion signal is outputted, whereby an errorcode to be outputted from the error code adding circuit 408 is added toa signal to be transferred and outputted via the output circuit 409subsequent to the error check code (error check code 2) which has beengenerated and outputted from the error check code generating circuit 407(see FIGS. 2(h) and (i)).

Thereafter, on completion of addition of the error code in the errorcode adding circuit 408, an error code adding completion signal istransmitted to the second switch circuit SW2 (see FIGS. 2(i) and (f)),whereby the second switch circuit SW2 is shifted to assume the initialstate, i.e., a state wherein inputting via the terminal 1 is selected(see FIG. 2(h)).

As the node controller 42 operates in the above-described manner, anerror code for informing that an error has occurred is favorably addedto the signal S2 to be transferred and outputted from the nodecontroller 42 to the node controller 43 at the next stage. With respectto node controllers located downstream of the node controller 43, theerror code which has been added in that way via the error code detectingcircuit 404 is detected such that an output from the OR circuit OR atthe time of outputting of the error check code outputting completionsignal is set to the logical "1" level based on the aforementioneddetection. This causes a signal having the error code added thereto tobe transferred and outputted from all the node controllers locateddownstream of the node controller 43.

FIG. 3 typically shows a plurality of signal transmission protocolsbased on the above-described presumption with respect to a series ofsignals S0, S1, S2, S3, --- Sn to be transmitted between the respectivenode controllers (see FIG. 10) (representing that an error has occurredbetween the node controller 41 and the node controller 42). As isapparent from the protocols in FIG. 3, the respective signals S1, S2,S3, --- Sn are transmitted from the nodes 41, 42, 43, --- 4n withconfigurations shown in FIGS. 3(b), (c), (d) and (e) in response totransmission of the signal S0 having a configuration shown in FIG. 3(a)from the main controller 30, by repeatedly executing the aforementionedoperations in the respective node controllers 41 to 4n.

It should be added that only the signal Sn outputted from the last nodecontroller 4n is taken in the main controller 30. A machine controller10 (see FIG. 10) confirms an occurrence of error in the apparatus basedon the error code which has been added to the signal Sn which has beentaken in the main controller 30.

In such manner, according to the embodiment of the present invention,even in a case where a series of signals S0 to Sn are transmittedwithout time delay between adjacent node controllers, i.e., even in acase where times T₀₀ to T_(n3) additionally noted to the respectiveprotocols shown in FIG. 3 are determined in accordance with thefollowing relationship among the times T₀₀ to T_(n3),

    T.sub.00 =T.sub.11 =T.sub.21 =T.sub.31 =T.sub.n1

the apparatus can effectively inform an occurrence of error of all thenode controllers inclusive of the main controller 30. Generally, in acase where at least the following relationship of inequalities ismaintained with respect to the aforementioned times T₀₀ to T_(n3), theabove-described method of informing an occurrence of error in accordancewith the embodiment of the present invention is effectively employablefor the apparatus.

    T.sub.11 <T.sub.01, T.sub.21 <T.sub.12, T.sub.31 <T.sub.22 ---

According to the embodiment of the present invention, the maincontroller 30 (machine controller 10) can be informed of an occurrenceof error in the apparatus based on the error code added to the signal Snwhich has been outputted from the node controller 4n having a port NO. n(at stage NO. n) but can not be informed as to at what part or locationthe error has occurred.

FIGS. 4 to 6 show an apparatus for carrying out serial control inaccordance with other embodiment of the present invention wherein theapparatus makes it possible with the foregoing problem in the firstembodiment in mind to allow the main controller 30 to be effectivelyinformed of the location where an error has occurred.

Specifically, in this embodiment, FIG. 4 illustrates by way of exampleconcrete structure of the respective node controllers 41 to 4n on theassumption that the apparatus is basically constructed as shown in FIG.10 in the same manner as in the embodiment in FIG. 1, FIG. 5 illustratesby way of example operations to be performed by the node controllershown in FIG. 4, and FIG. 6 illustrates by way of example a plurality ofprotocols particularly employable for respective transmitted signals inthis embodiment. Also in this embodiment, a method of transmittingsignals in connection with illustration in FIG. 5 and FIG. 6 as well asa presumption on an occurrence of error are described as one examplebelow in the same manner as in the first embodiment based on theassumption of a method of transmitting signals without time delaybetween the respective node controllers as well as an occurrence oferror during signal transmission between the node controller 41 and thenode controller 42. Referring to FIG. 4 again, the same circuits asthose in FIG. 1 are identified by same reference numerals. Thus,repeated description will not be required.

According to this embodiment, as shown in FIG. 4, each of the nodecontrollers 41 to 4n is provided with a four input selection type switchcircuit SW2' as a second switch circuit. Further, it includes an errorport end detecting circuit 411 and an error port adding circuit 412.

The error port adding circuit 412 is provided in the form of a circuitadapted to add a signal having a logical "1" level by a quantity of,e.g., one bit via an input terminal 4 of the second switch circuit SW2'subsequent to the error code as an error port information for allowingthe main controller 30 (machine controller 10) to identify the port(node controller 42 in this embodiment) where an occurrence of error hasbeen confirmed. After completion of an operation for adding an errorport information, the error port adding circuit 412 operates to transmitan error port adding completion signal to the second switch circuitSW2'.

The error port end detecting circuit 411 is provided in the form of acircuit adapted to be activated in response to an output derived fromdetection of an error code by the error code detecting circuit 404 todetect the error port information to be added subsequent to the errorcode as well as a location where the error port information isinterrupted, i.e., an error port information end, in a case where asignal row inputted into its own port (exactly speaking, signal rowinputted and demodulated by the input circuit 401) includes an errorcode. In response to detection of the error port end information, theerror port end detecting circuit 411 operates to output to the secondswitch circuit SW2' a detection signal which represents that the errorport end information has been detected.

A selecting (shifting) operation of the second switch circuit SW2' islogically preset in the following manner. In detail, while the secondswitch circuit SW2' is held in its initial state, as shown in FIG. 5(j),it assumes a state wherein inputting via a terminal 1 is selected (itshould be noted that an inputted/demodulated signal row is outputted viathe output circuit 409 as it is left unchanged, while the foregoingstate is maintained). When the second switch circuit SW2' receives anoutput derived from detection of a stop code (see FIG. 5(c)), it assumesa state wherein inputting via a terminal 2 is selected (it should benoted that the error check code which has been newly generated andoutputted via the error check code generating circuit 407 is outputtedvia the output circuit 409, while the foregoing state is maintained).When an output from the OR circuit OR is held at a logical "0" levelbased on the present logical level representative of an output from theOR circuit OR at the time when the second switch circuit SW2' receivesan error check outputting completion signal (i.e., at the time when noerror occurs) (see FIG. 5(f)), it assumes the initial state, i.e., astate wherein inputting via the terminal 1 is selected. Similarly, whenan output from the OR circuit OR is held at a logical "1" level (i.e.,when an occurrence of error is confirmed or when an error has heretoforeoccurred), the second switch circuit SW2' assumes a state whereininputting via a terminal 3 is selected (it should be noted that theerror code outputted from the error code adding circuit 408 is outputtedvia the output circuit 409). When an output derived from detection ofthe error code detecting circuit 404 (output derived from the OR circuitOR) is held at a logical "0" level based on the logical levelrepresentative of the output from the error code detecting circuit 404at the time when the second switch circuit SW2' receives an error codeadding completion signal (see FIG. 5(g)), it assumes a state whereininputting via a terminal 4 is selected (it should be noted that an errorport information "1" outputted from the error port adding circuit 412 isdelivered via the output circuit 409, while the foregoing state ismaintained). Similarly, when an output from the OR circuit OR is held ata logical "1" level, the second switch circuit SW2' once assumes theinitial state, i.e., a state wherein inputting via the terminal 1 isselected (at this time, it should be noted that the error portinformation added to the signal row till the node controller at thepreceding stage is delivered via the output circuit 409). Then, thesecond switch circuit SW2' assumes a state wherein inputting via theterminal 4 is selected, only when it receives a detection signal fromthe error port end detecting circuit 411. In addition, when the secondswitch circuit SW2' receives an error port adding completion signal fromthe error port adding circuit 412 (see FIGS. 5(k) and (h)), it isrestored to the initial state, i.e, a state wherein inputting via theterminal 1 is selected.

Therefore, in a case where an error occurs between the node controller41 and the node controller 42 and the occurrence of error is confirmedby the node controller 42 in the same manner as in the above-describedembodiment, the second switch circuit SW2' and associated circuitsoperate in response to inputting of a signal S1 having no error codeadded thereto, as represented by a plurality of timing charts in FIG. 5(see FIG. 5(a)), whereby an error code information and an error portinformation are added to the node controller 42 in such a manner asshown in FIG. 5(k) and they are then outputted to the node controller 43at the next stage as a signal S2, respectively. This causes the nodecontroller 43 to detect the error code information end and the errorport information end which have been added thereto in such a manner asrepresented by dotted lines in FIGS. 5(a) and (b), whereby a signal S3to be transmitted to a node controller 44 at the next stage is outputtedfurther based on the selecting operation of the second switch SW2' insuch a manner as shown in FIG. 6(d). With respect to node controllerslocated downstream of the node controller 44, same processings arerepeatedly executed. Consequently, a plurality of protocols for a seriesof signals S0 to Sn to be transmitted between the respective nodecontrollers are determined in such a manner as typically shown in FIG.6.

According to the embodiment of the present invention, what is taken inthe main controller 30 is only the signal Sn which has been outputtedfrom the node controller 4n at the final stage, like in the precedingembodiment. In a case of this embodiment, however, the main controller30 (machine controller 10) can recognize a location (port) where anerror has occurred, based on the error code information and the errorport information having (n-1) bits added to the signal Sn (see FIG.6(e)), at the same time when an error has occurred in the apparatus.Thus, with the apparatus of the present invention having the number n ofports (corresponding to the node controllers 41 to 4n ) in addition tothe main controller 30, in a case where the port NO. k (the second portin the preceding embodiment) confirms a first occurrence of error, themachine controller 10 can know an address k of the port NO. k which hasconfirmed the occurrence of error, based on the error port informationhaving (n-k+1) bits.

In this manner, according to the embodiment of the present inventionshown in FIGS. 4 to 6, the apparatus can effectively inform all the nodecontrollers including the main controller 30 of an occurrence of error,even in a case where a series of signals S0 to Sn are transmittedbetween the respective node controllers without time delay in the samemanner as in the preceding embodiment. At the same time, the apparatuscan inform the main controller 30 (machine controller 10) of a locationwhere an error has occurred.

FIGS. 7 to 9 schematically illustrate an apparatus for carrying outserial control in accordance with another embodiment of the presentinvention, respectively, wherein a function of informing a locationwhere an error occurs as described above with respect to the embodimentshown in FIGS. 4 to 6 has been improved further. According to thisembodiment, the function of informing a location where an error occurscan be realized at a high efficiency by reducing the number of bitsrepresentative of error port informations.

In this embodiment, FIG. 7 illustrate by way of example concretestructure of the respective node controllers 41 to 4n on the assumptionthat the apparatus is basically constructed as shown in FIG. 10 in thesame manner as in FIG. 1 or FIG. 4, and FIGS. 8 and 9 illustrate by wayof example operations to be performed by the node controllers 41 to 4nshown in FIG. 7, respectively. Also in this embodiment, assumption on amethod of transmitting signals in connection with illustration in FIG. 8and FIG. 9 as well as an occurrence of error is made in the same manneras in the aforementioned embodiments based on the presumption of, e.g.,a method of transmitting signals without time delay in each nodecontroller as well as an occurrence of error during transmission ofsignals between the node controller 41 and the node controller 42.Referring to FIG. 7 again, the same circuits as those in FIG. 1 areidentified by same reference numerals. Thus, repeated description onthese circuits will not be required.

As shown in FIG. 7, according to the embodiment of the presentinvention, each of the node controllers 41 to 4n includes an error portcord forming circuit 413 for additionally forming an error port code atthe tail end of a signal to be transmitted to the output circuit 409with structure as shown in FIG. 7 to indicate a location where an erroroccurs in a case where an error code is detected from theinputted/demodulated signal and an error port code position detectingcircuit 414 for detecting a position where an error port code to thesignal to be transmitted (addition timing), i.e., a position assumed bythe tail end of an error code of the signal to be transmitted (signal tobe outputted from the second switch circuit SW2) in addition to therespective circuits shown in FIG. 1.

With the error port code position detecting circuit 414, detection ofthe position where the error port code is added (position assumed by thetail end of the error code) is carried out, e.g., in such a manner thata stop code of the signal to be transmitted (signal outputted from thesecond switch circuit SW2) is once detected and a position where theerror port code is added is then determined after a predetermined bittime (period) elapses. Thus, with the apparatus of the presentinvention, when it is assumed that the number of bits of the error codeis set to, e.g., 8 bits and the number of bits of the error check codeis set to, e.g., 16 bits, the position (timing) assumed when a period oftime elapses by 24 bits (16 bits +8 bits) after detection of the stopcode represents a position (addition timing) where the error port codewhich has been detected is to be added. Further, the error port codeposition detecting circuit 414 outputs an one shot-shaped pulse signalin synchronization with detection (determination) of the error port codeadding position. Such a manner of outputting detection as describedabove is same with other detecting circuits 402, 404 and 408.

FIG. 8 shows a plurality of timing charts which illustrate by way ofexample operations to be performed by one of the node controllers 41 to4n, e.g., a node controller 42. In fact, operations to be performed bythe node controller 42 partially overlap operations to be performed bythe apparatus in accordance with the embodiment shown in FIGS. 1 to 3depending on the state of the signal row to be transmitted. In view ofthe foregoing fact, signal processing operations to be executed by eachnode controller will be described below in more details with referenceto FIG. 8.

Now, it is assumed that a signal as shown in FIG. 8(a) is transmittedfrom a node controller at the preceding stage (node controller 41) to anode controller at the next stage (node controller 42) and it is theninputted and demodulated in the input circuit 401. The start codedetecting circuit 402 detects a start code in the input signal row in atiming relationship shown in FIG. 8(b) to control a shifting operationfor turning on the first switch circuit SW1 (which has been turned offat the initial time)(see FIG. 8(g)). This allows the error check codegenerating circuit 407 to start an operation for generating an errorcheck code to be transmitted to a node controller at the next stage(node controller 43) based on the signal row which has been inputtedinto the error check code generating circuit 407 (mainly, data row).Incidentally, at this time, the second switch circuit SW2 is held in theinitial state, i.e., a state wherein inputting via a terminal 1 isselected, as shown in FIG. 8(h), whereby the start code and the data roware added to the output circuit 409 via the second switch circuit SW2 asthey are left unchanged and they are then transferred and outputted tothe node controller at the next stage (node controller 43) via theoutput circuit 409 (see FIGS. 8(h) and (i)). In the meantime, the dataconverting circuit 405 executes a data converting operation between thecorresponding sensors or actuators (22).

As the signal row is transmitted in that way, the stop code detectingcircuit 406 detects a stop code in a timing relationship as shown inFIG. 8(c).

When the stop code detecting circuit 406 detects the stop code in thatway, it controls a shifting operation for shifting the first switchcircuit SW1 to the initial state, i.e., an OFF state and shifting thesecond switch circuit SW2 to a state wherein inputting via a terminal 2is selected (see FIGS. 8(c), (g) and (h)).

In response to shifting of the second switch circuit SW2 in that way,the error check code 2 which has been newly generated in the error checkcode generating circuit 407 is selected from the second switch circuitSW2 subsequent to the stop code which has been already selected and itis then transferred via the output circuit 409 (see FIG. 8(i)).

At the same time, the error checking circuit 403 executes an inspectingoperation with respect to the error check code (error check code 1)which has been transferred from the node controller .at the precedingstage (node controller 41). If no data error occurs, no signal isoutputted from the error checking circuit 403 but, in a case where anoccurrence of error is confirmed by the error checking code as ispresumed here, an error detecting signal held at a logical "1" level isoutputted from the error checking circuit 403 for a short period of timeat the same time as confirmation of the occurrence of error (see FIG.8(d)). Therefore, an output from an OR circuit OR1 is also held at alogical "1" level for the foregoing period of time (for a period of timewhen an error detecting signal is outputted). The output from the ORcircuit OR1 is added to the second switch circuit SW2 together with anerror check code outputting completion signal which has been generatedon completion of outputting of the error check code generated by theerror check code generating circuit 407 (see FIGS. 8(i) and (e)).

The second switch circuit SW2 is provided in the form of a switchcircuit adapted to control a shifting operation depending on the logicallevel of a signal to be added from the OR circuit OR to assume theinitial state, i.e., a state wherein inputting via the terminal 1 isselected when the foregoing logical level is held at a logical "0" levelor assume a state wherein inputting via a terminal 3 is selected whenthe foregoing logical state is held at a logical "1" level, under acondition that an outputting completion signal representative of theerror check code is added from the error check code generating circuit407, as described above. Therefore, in this case, at the same time whenan error check code outputting completion signal is generated, thesecond switch circuit SW2 assumes a state wherein inputting via theterminal 3 is selected, whereby an error code to be outputted from theerror code adding circuit 408 is added to the signal which has beentransferred and outputted via the output circuit 409, subsequent to theerror check code (error check code 2) which has been generated andoutputted from the error check code generating circuit 407 (see FIGS.8(h) and (i)).

Thereafter, on completion of adding of the error code, the error codeadding circuit 408 transmits an error code adding completion signal tothe second switch circuit SW2 (see FIGS. 8(i) and (f)) so that thesecond switch circuit SW2 is brought in the initial state. i.e., a statewherein inputting via the terminal 1 is selected (see FIG. 8(h)).

As a result derived from the aforementioned operations of the nodecontroller 42, an error code for informing that the node controller 42is held in a state wherein an error has occurred is favorably added tothe signal S2 to be transferred and outputted from the node controller42 to the node controller 43 at the next stage. In the meantime, anyerror code is not detected from the inputted/demodulated signal derivedfrom the input circuit 401 in the node controller 42. Therefore, a NANDcondition for an NAND circuit ND is not established also in the errorport code forming circuit 413 (in this case, it should be noted that aFlip-Flop FF2 is set but a Flip-Flop FF1 is not set), whereby a signaloutputted from the second switch circuit SW2 is added to the outputcircuit 409 as it is left unchanged, via an AND circuit (AND gate) AD1and an OR circuit (OR gate) OR2.

Next, operations of the apparatus in accordance with the embodiment ofthe present invention will be described below with reference to FIG. 9as to the node controller 43 inclusive of other node controllers locateddownstream of the node controller 43.

First, the node controller 43 carries out detection of a start code inresponse to the signal S2 inputted via the input circuit 401 and thendemodulated (see FIG. 9(a)), inputting/outputting of corresponding data,detection of a start code, inspection of error check code 2 (errorcheck) and generation and addition of a new error check code 3 in thesame manner as operation with the node controller 42. Thereafter, thenode controller 403 detects an error code to be added via the error codedetecting circuit 404 (see FIG. 9(b)). The node controller 403 holds anoutput from the OR circuit OR1 at a logical "1" level based on detectionof the error code in the same manner as described above, when an errorcheck code outputting completion signal (see FIG. 8(c)) is transmittedfrom the node controller at the present stage. This causes a signalhaving an error code added thereto to be outputted from the nodecontroller 43 in response to the same operation of the switch circuitSW2 as described above.

In addition, the node controller 43 allows the Flip-Flop FF1 in theerror port code forming circuit 413 to be set in response to detectionof the error code (see FIG. 9(b)). Further, the node controller 43allows the Flip-Flop FF2 in the error port code forming circuit 413 tobe set at the time when the error port code position detecting circuit414 detects an error port code position (error code end position) (seeFIG. 9(c)). This enables the NAND condition of the NAND circuit ND inthe error port code forming circuit 413 to be settled satisfactorily,whereby the AND circuit (AND gate) AD1 is closed and the AND circuit(AND gate) AD2 is opened at the same time when the NAND conditions issettled. Thus, a signal outputted from the second switch circuit SW2 inthe node controller 43 is added to the output circuit 409 via the ANDcircuit AD2 and the OR circuit OR2 in the form of a signal logicallyinverted by an inverter INV, at the time when the NAND condition hasbeen settled (at the time when the error code position has beendetected). In this case, it should be added that the signal level justbehind the error code added in that way is held at a logical "1" levelin response to receiving of a signal to be added to the output circuit409 and then transferred and outputted to a node controller at the nextstage (node controller 44) via the output circuit 409 (see FIG. 9(f)).

When a signal outputted from the OR circuit OR2 is held at a logical "1"level in the above-described manner, an AND condition of an AND circuitAD3 is established in response to outputting of the preset Flip-FlopsFF1 and FF2 (held at a logical "1" level), whereby a Flip-Flop FF3serving as a third Flip-Flop is brought in a set state (see FIG. 9(d)).A set output from a Flip-Flop FF3 is delayed by an one-bit delay circuitDL for a period of time represented by one bit time and added torespective reset terminals R of the Flip-Flop FF1, the Flip-Flop FF2 andthe Flip-Flop FF3, causing the Flip-Flop FF1, the Flip-Flop FF2 and theFlip-Flop FF3 to be reset (see FIGS. 9(e), (b), (c) and (d)).Specifically, in a case where a part of the signal outputted from the ORcircuit OR2 and located behind the position of the error port is broughtin a logical "1" level and thereby the AND condition of the AND circuitAD3 is settled, the NAND condition of the NAND circuit ND fails to besettled after the signal held at the logical "1" level is maintained fora period of time represented by one bit so that the signal to beoutputted from the second switch circuit SW2 is added again to theoutput circuit 409 via the AND circuit AD1 and the OR circuit OR2 fromthe aforementioned time point.

With respect to the signal S2 inputted in the node controller 43 in sucha manner as shown in FIG. 9(a) under the function of the second switchcircuit SW2 and the error port code forming circuit 413, an error codeis subsequently added to the error check code 3 which has been newlygenerated in response to the signal S2 in the same manner as describedabove. Thereafter, an error port code "1" is added to the error checkcode 3 in such a manner as shown in FIG. 9(f), and the signal having theerror code and the error port code "1" added thereto is transferred tothe node controller 44 at the next stage as an output signal S3 from thenode controller 43.

In this manner, the second switch circuit SW2 at each node controllerexecutes the following operations.

A) In a case where any error or any error code is not detected from aninput signal to be inputted into the relevant node controller, thesecond switch circuit SW2 outputs to the output circuit 409 a set ofserial signals to be transmitted, each signal including a start code, adata row, a stop code and an error check code generated by the errorcheck code forming circuit 407 in the node controller at the presentstage.

B) In a case where an error or an error code is detected from the inputsignal, the second switch circuit SW2 adds the error code to the tailend of a signal row and outputs to the output circuit 409 a set ofserial signals to be transmitted, each signal including a plurality ofcodes ranging from the start code till the error code.

Next, the error port code forming circuit 413 executes the followingoperations.

a) In a case where no error code is detected from an input signal to beinputted into a relevant node controller, the error port code formingcircuit 413 transmits an output signal from the second switch circuitSW2 to the output circuit 409 as it is left unchanged, while the ANDcircuit (AND gate) AD1 side is kept opened (the AND circuit AD2 side iskept closed).

b) In a case where an error code is detected from the input signal, theerror port code forming circuit 413 once opens the AND circuit (ANDgate) AD2 side (the AND circuit AD1 side is closed), at the time when anerror port code position (error code tail end position) is detectedtogether. Then, a part of the output signal from the second switchcircuit SW2 located behind the error port code position is logicallyinverted by the inverter INV and then transmitted to the output circuit409.

c) When a logical level for signals to be transmitted in a logicallyinverted state reaches a logical level "1", the error port code formingcircuit 413 opens the AND circuit AD1 side again. Then, a part of theoutput signal from the second switch circuit SW2 located behind thesecond switch circuit SW2 is outputted to the output circuit as it isleft unchanged.

Consequently, according to the embodiment of the present invention, anerror code and an error port code are successively added also to aseries of signals S4 to Sn outputted from node controllers locateddownstream of the node controller 44 in such a manner as shown in FIGS.9(g) to (m).

Here, it will be significant that attention is paid to signals which areformed and added behind the error code as an error port code.

As will be apparent from FIG. 9(a) and FIGS. (f) to (l) which illustrateoperations to be performed by the error port code forming circuit 413,the signal constituting the error port code is provided in the form of asignal including a logical structure of the type which is successivelysubjected to binary addition by a quantity of "1" at every time when itpasses through a node controller at the next stage from the port (nodecontroller 42) which has confirmed an occurrence of error.

With such structure, e.g., the error port code "1" of a signal S3 shownin FIG. 9(f) is represented by the following equation using decimalnumerals.

    1×2.sup.0 =1

Similarly, the error port code "01" of a signal S4 shown in FIG. 9(g) isrepresented by the following equation.

    0×2.sup.0 +1×2.sup.1 =2

Further, similarly, the error port code "111" of a signal S9 shown inFIG. 9(l) is represented by the following equation.

    1×2.sup.0 +1×2.sup.1 +1×2.sup.2 =7

Therefore, when it is assumed that the number n of node controllers is9, i.e., n=9 and the signal S9 shown in FIG. 9(l) is taken in the maincontroller 30, the main controller 30 can recognize that the portrepresented by the following equation derived from reverse calculation,i.e., the node controller 42 is "a port which has confirmed anoccurrence of error".

    7+1=8

It should of course be understood that the above result coincides withthe preset assumption (an error occurs during transmission of signalsbetween the node controller 41 and the node controller 42, i.e., anoccurrence of error is confirmed at the node controller 42). In a caseof the foregoing embodiment, a code length of the error port code isrepresented by the following term with respect to the number n of nodecontrollers, i.e., the number n of ports.

    log.sub.2 n (bits)

For example, in a case where the number of ports is 100, i.e., n=100,the code length is represented by 7 bits (log₂ 100/6.6).

In this manner, according to the embodiment of the present invention,even in a case where a series of signals S0 to Sn are transmittedbetween the respective node controllers without time delay, theapparatus can effectively inform all the node controller including themain controller 30 of an occurrence of error. Particularly, theapparatus can inform the main controller 30 (machine controller 10) alsoof a location where an error occurs, at a high efficiency at the sametime as the aforementioned information.

Further, according to the above-described embodiment, the error portcode forming circuit 413 and associated components are constructed asshown in FIG. 7. However, the present invention should not be limitedonly to this. Alternatively, another structure modified in the followingmanner may be employed for the error port code forming circuit 413 andassociated components shown in FIG. 7.

A logical sum of an error code adding completion signal outputted fromthe error code adding circuit 408 (see FIG. 8(f) and an error codedetecting output outputted is added to a set terminal S of the Flip-FlopFF1.

In this case, the port (node controller) which has confirmed anoccurrence of error starts formation and addition of an error port code.Therefore, in a case of the aforementioned example, the output signal S2from the node controller 42 becomes a signal including an error portcode "1" as shown in FIG. 9(f) and the output signal S3 from the nodecontroller 43 becomes a signal including an error port code "01".Similarly, later output signals following the output signal S3 becomesuch a signal that the content of binary addition of an error port codeto be added to the signal shifts successively. Thus, in this case, themain controller 30 recognizes that the port located upstream of the portNO. n by a value represented by way of reverse calculation by a decimalnumeral representative of an error port code outputted therefrom is "aport which has confirmed an occurrence of error".

Structure of the error port code forming circuit 413 shown in connectionwith the above-described embodiment is merely illustrative but thepresent invention should not be limited only to this. Basically, anystructure, of course, may be employed for the error port code formingcircuit 413, if it is proven that signal protocols as shown in FIGS. 8and 9 or signal protocols similar those in the drawings are practicallyassured.

In addition, structure of the node controllers 41 to 4n shown inconnection with the respective embodiments as described above (FIG. 1,FIG. 4 and FIG. 7) is merely illustrative but the present inventionshould not be limited only to this. Alternatively, any other structuremay be employed for the node controllers 41 to 4n, if it is proven thatsignal protocols corresponding to the respective node controllers arepractically assured.

For example, according to these embodiments, the stop code detectingcircuit 406 is disposed rearward of the data converting circuit 405thereby to detect a stop code from the signal row having sensor dataadded thereto or having actuator control data removed therefrom.However, in a case where a data row length of the data row does not varywhen data are added or removed by the data converting circuit 405 (i.e.in a case where a data row length does not vary even by employing dummydata or the like medium), the stop code detecting circuit 406 may bedisposed rearward of the input circuit 401 in the same manner as thestart code detecting circuit 402 and the error check circuit 403.

The sensors or the actuators to be controlled by the respective nodecontrollers 41 to 4n are not required to be one of the sensors oractuators. Alternatively, they may be plural ones of the sensors oractuators or a mixture of the sensors and the actuators. Structure ofthe data converting circuit 405 is determined depending on structure ofterminal components associated with the node controller to becontrolled.

In any one of the aforementioned embodiments, description has been madeas to structure of the node controllers and protocols for transmittingsignals in a case where the present invention is applied to an apparatusfor carrying out serial control wherein the main controller 30 and thenode controllers 41 to 4n are serially connected to each other in aloop-shaped configuration in such a manner as shown in FIG. 10. However,in a case where a plurality of sensors are to be controlled by each nodecontroller, the present invention may equally be applied to an apparatusfor carrying out serial control wherein the main controller 30 and thenode controllers 41 to 4n are serially connected to each other in aso-called daisy fashion with the main controller 30 serving as a finalstage. In this case, only the node controller (node controller 41)disposed at the head end of arrangement of the node controllers is addedwith a function of generating a signal row shown in, e.g., FIG. 11(b) orFIG. 3(b) (i.e., FIG. 2(a)) or FIG. 6(b) (i.e., FIG. 5(a)) or FIG. 8(a).With respect to all other components, the same structure for nodecontrollers and the same protocols for transmitting signals as describedabove may be employed for the apparatus.

INDUSTRIAL APPLICABILITY

As will be readily apparent from the above description, the presentinvention provides many advantageous effects as noted below.

(1) The apparatus can reliably inform all necessary node controllers ofan occurrence of error without reduction of an operative efficiency fortransmitting data in the form of data link.

(2) For the reason as described in the preceding paragraph (1), theapparatus can effectively prevent respective sensors or actuators to becontrolled from being incorrectly informed or incorrectly operated.

(3) Each node controller itself does not require any particular addressor the like means. Consequently, all components required for theapparatus can be fabricated in common design and dimensions withadvantageous effects derived from mass production.

(4) For the reason as described in the preceding paragraph (3), theapparatus does not require any consideration on a signal transmissionsystem when sensors or actuators are added, removed or replaced. Thus, amachine for which the apparatus is arranged can be rebuilt orreconstructed with easiness.

We claim:
 1. An apparatus for carrying out serial control, wherein saidapparatus includes;a main controller for centrally controlling data 1received from a number of sensors or data to be transmitted to a numberof actuators and a plurality of node controllers serially connected tosaid main controller, each of said node controllers being disposedcorresponding to one or plural ones of said sensors or said actuators sothat a data signal row including at least an error check code isinputted thereinto, an occurrence of error is monitored with respect tosaid data signal row based on said error check code, data aretransmitted from the node controller to the corresponding sensors oractuators and vice versa and the data signal row is transferred to anext port,and wherein each node controller includes; error checkingmeans for detecting an occurrence of error based on an error check codein the inputted data signal row, error code detecting means fordetecting an error code indicative of an occurrence of error, in a casewhere said error code is added to the data signal row and error codeadding means for adding the error code to the data signal row to betransferred to the next port, when the presence of an output derivedfrom detection by said error checking means or the presence of an outputderived from detection by said error detecting means is found.
 2. Anapparatus for carrying out serial control as claimed in claim 1, whereineach of said node controllers further includes means for adding to thedata signal row an error port information which is to be successivelyadded by a quantity of one bit at every time said error port informationpasses through the node controller from the port where an error hasoccurred, said error port information being provided in the form of asignal having a specific logic with one bit as an unit to be addedsubsequent to the error code.
 3. An apparatus for carrying out serialcontrol as claimed in claim 1, wherein each of said node controllerfurther includes means for adding to the data signal row an error portinformation which is to be successively added from the least significantbit, means for providing said error port information in the form of acode information to be added subsequent to the error code, said errorport information having a logical structure of such a type that meansare provided for subjecting it to binary addition by a quantity of 1 atevery time it passes through the node controller from the port where anerror has occurred.